1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a capacitor structure of a semiconductor device applicable to a storage capacitor of a semiconductor memory device, and a method of fabricating the same.
2. Description of the Prior Art
Storage capacitors are one of the main components of the memory cell of a semiconductor memory device.
In general, the output voltage from the memory cell is proportional to the capacitance value of the storage capacitor of the cell and thereof, the capacitor need to have a satisfactorily large capacitance value to ensure stable operation of the cell or to improve the operation reliability of the cell. On the other hand, the capacitor needs to be further miniaturized with the recent progressing miniaturization and integration of the cell. Thus, in recent years, there has been the strong need to develop new capacitor structures that make it possible to realize a satisfactorily large capacitance value even if the cell is further miniaturized. To meet this need, various capacitor structures have been developed and disclosed, one of which is shown in FIG. 1.
FIG. 1 shows a part of the memory cells of a semiconductor memory device, in which prior-art storage capacitors 130 are formed on the surface of a semiconductor substrate 101 along with Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) 131. One of the MOSFETs 131 and a corresponding one of the capacitors 130 constitute the cell.
An isolation dielectric 102 is selectively formed on the surface of the substrate 101, defining active areas (not shown) thereon. In each of the active areas, a gate insulator 120 is selectively formed on the surface of the substrate 101, a gate electrode 103 is formed on the gate insulator 120, and a pair of source/drain regions 121a and 121b are formed in the substrate 101 at each side of the gate electrode 103. The pair of source/drain regions 121a and 121b, the gate insulator 120, and the gate electrode 103 constitute the MOSFET 131 in each of the active areas.
A first interlayer dielectric layer 104 is formed to cover the isolation dielectric 102, the gate electrodes 103, and the pairs of exposed source/drain regions 121a and 121b. A second interlayer dielectric layer 105 is formed on the first interlayer dielectric layer 104. The layer 105 is thicker than the first interlayer dielectric layer 104, because a wiring layer 106 is formed in the layer 105. The wiring layer 106 is electrically connected to the respective source/drain regions 121a. The wiring layer 106 does not appear in the cross-section of the device shown on FIG. 1 and thus, it is illustrated by broken lines.
A silicon nitride (SiN.sub.x) layer 107 is formed on the second interlayer dielectric layer 105. The layer 107 serves as an etch stop layer in the process of etching the layers overlying the layer 107.
Contact holes 122 are formed to penetrate the SiN.sub.x layer 107 and the second and first interlayer dielectric layers 105 and 104. The holes 122 reach the corresponding source/drain regions 121b, exposing the same. The holes 122 are filled with conductive contact plugs 117. The bottoms of the plugs 117 are contacted with and electrically connected to the corresponding source/drain regions 121b.
Lower electrodes 116, which serve a charge storage electrodes of the respective memory cells, are formed on the SiN.sub.x layer 107 to be overlapped with the respective active areas. These electrodes 116 are separated from each other by small gaps. As seen from FIG. 1, each of the electrodes 116 is formed by a circular-plate-shaped bottom. 116a and a cylindrical sidewall 116b connected to the periphery of the bottom 116a. The sidewall 116b extend upward from the periphery of the bottom 116a. The center of the bottom 116a is contacted with and electrically connected to the top of a corresponding one of the contact plugs 117.
A capacitor dielectric 114 is formed to cover all the lower electrodes 116. The dielectric 114 is contacted with not only the exposed areas of the electrodes 116 but also those of the silicon nitride layer 107 exposed from the gaps between the electrodes 116. The dielectric 114 is commonly used for all the electrodes 116.
An upper electrode 115 is formed on the capacitor dielectric 114 to be opposite to all the lower electrodes 116. The electrode 115 is commonly used for all the electrodes 116. The electrode 115 extends along the dielectric 114.
The upper electrode 115, the capacitor dielectric 114, and one of the lower electrodes 116 constitute each of the storage capacitors 130. Each of the MOSFETs 131 and a corresponding one of the capacitors 130 constitute the memory cell.
Next, a method of fabricating the prior-art semiconductor memory device shown in FIG. 1 is explained below with reference to FIGS. 2A to 2H.
First, as shown in FIG. 2A, the isolation dielectric 102, which is made of silicon dioxide (SiO.sub.2), is selectively formed on the surface of the semiconductor substrate 101, thereby defining the active areas. Next, a SiO.sub.2 layer (not shown) is formed on the whole surface of the substrate 101 and an impurity-doped polysilicon layer (not shown) is deposited on the SiO.sub.2 layer thus formed. The SiO.sub.2 and polysilicon layers are patterned to have a specific shape, thereby forming the gate insulators 120 and the gate electrodes 103 on the surface of the substrate 101 in the respective active areas.
Using the isolation dielectric 102 and the gate electrodes 102 as a mask, an impurity is selectively implanted into the substrate 101, thereby forming the pairs of the source/drain regions 121a and 121b in the respective active areas. Each pair of source/drain regions 121a and 121b is located in self-alignment with respect to a corresponding one of the gate electrodes 103.
Thus, the MOSFETs 131 are fabricated on the substrate 101, each which is formed by one of the pairs of source/drain regions 121a and 121b, a corresponding one of the gate insulators 120, and a corresponding one of the gate electrodes 103.
Subsequently, the first interlayer dielectric layer 104, which is made of SiO.sub.2, is formed to cover the whole surface of the substrate 101. At this time, the isolation dielectric 102 and the MOSFETs 131 are covered with the layer 104, Then, the second interlayer dielectric layer 105, which is made of BoroPhospoSilicate Glass (BPSG), is formed on the first interlayer dielectric layer 104. The layer 105 contains in its inside the wiring layer 106 electrically connected to the respective source/drain regions 121a. The SiN.sub.x layer 107 is formed on the second interlayer dielectric layer 105 thus formed by a Chemical Vapor Deposition (CVD) method.
On the SiN.sub.x layer 107 thus formed, a patterned resist film 109 having openings 109a is formed. The openings 109a are used for forming the contact holes 122 and located at positions right over the respective source/drain regions 121b. The state at this stage is shown in FIG. 2A.
Following this step, using the patterned resist film 109 as a mask, the SiN.sub.x layer 107 and the second and first interlayer dielectric layers 105 and 104 are etched selectively and successively. Thus, as shown in FIG. 2B, the contact holes 122 are formed to penetrate the layers 107, 105, and 104, exposing the underlying source/drain regions 121b. Thereafter, the resist film 109 is removed.
A first conductive layer (not shown) having a thickness large enough for filling the contact holes 122 is formed on the SiN.sub.x layer 107. As the first conductive layer, for example, an impurity-doped (i.e., n- or p-type) polysilicon layer is used. The first conductive layer thus formed is then etched back until the underlying SiN.sub.x layer 107 is exposed, thereby leaving selectively the first conductive layer in the holes 122. Thus, as shown in FIG. 2C, the conductive contact plugs 117 are formed in the holes 122 by the remaining first conductive layer.
Subsequently, as shown in FIG. 2D, the first interlayer dielectric layer 108, which is made of SiO.sub.2, is formed on the SiN.sub.x layer 107. The layer 108 is contacted with the tops of the plugs 117. On the layer 108 thus formed, a patterned resist film 112 is then formed. The film 112 has openings 112a that expose selectively the areas where the lower electrodes 116 are to be formed. Using the film 112 as a mask, the first interlayer dielectric layer 108 is selectively etched to form a spacer layer 108a on the layer 107, as shown in FIG. 2E. The spacer layer 108a has openings 128 that expose the underlying SiN.sub.x layer 107 and the tops of the contact plugs 117, which is used for defining the lower electrodes 116.
Next, as shown in FIG. 2F, a second conductive layer 113, which is made of an impurity-doped (i.e., n- or p-type) polysilicon, is formed on the SiN.sub.x layer 107 to cover the spacer layer 108a and the exposed contact plugs 117. Then, a second dielectric layer 111, which is made of SiO.sub.2, is deposited on the layer 113 by a CVD method. The layer 111 has a thickness large enough for burying entirely the openings 128 of the layer 108a.
Thereafter, the second dielectric layer 111 and the second conductive layer 113 are successively etched back until the top of the spacer layer 108a is exposed. Thus, as shown in FIG. 2G, the parts of the layer 113 existing outside the openings 128 are selectively removed, leaving the layer 113 only in the opening 128. As a result, the lower electrodes 116 are formed on the SiN.sub.x layer 107 by the remaining parts of the layer 113.
To completely remove the spacer layer 108a and the remaining second dielectric layer 111, these layers 108a and 111 are further etched while the SiN.sub.x layer 108 is used as an etch stop layer. The state at this stage is shown in FIG. 2H.
Following this, as shown in FIG. 1, the capacitor dielectric 114, which has a layered structure of SiO.sub.2 and SiN.sub.x layers, is formed to cover the lower electrode 116. The dielectric 114 is contacted with the exposed areas of the SiN.sub.x layer 107 through the gaps between the electrodes 116.
Finally, as shown in FIG. 1, the upper electrode 115, which is made of an impurity-doped polysilicon, is formed on the capacitor dielectric 114. The electrode 115 extends along the dielectric 114. Thus, the prior-art semiconductor memory device with the storage capacitors 130 is fabricated.
As explained above, with the prior-art storage capacitor 131 shown in FIG. 1, the opposing area between the lower and upper electrodes 116 and 115 can be increased due to existence of the cylindrical sidewall 116b of the lower electrode 116, raising its capacitance value. However, a desired capacitance value that copes with further miniaturization and integration of the storage cell is unable to be accomplished.
Additionally, another prior-art structure of the storage capacitor is disclosed in the Japanese Non-Examined Patent Publication No. 9-275194 published in October 1997. In this structure, the lower electrode has a "double cylindrical structure" that the lower electrode has concentric inner and outer cylindrical parts and therefore, an obtainable capacitance value is larger than that of the prior-art capacitor structure shown in FIG. 1. Even in this structure, however, a desired capacitance value coping with further miniaturization and integration of the storage cells is unable to be accomplished.
In summary, with the above-explained prior-art capacitor structures, any satisfactory amount of electric charge becomes unable to be stored in the storage capacitor due to their unsatisfactory capacitance value according to the progressing miniaturization. As a result, there is a problem that stable operation of the memory cells cannot be ensured and consequently, the operation reliability of the semiconductor memory device degrades.